Continuously shrinking device features are setting increasingly high requirements for deposition and lithography techniques and will likely continue to do so in the future. For example, the high aspect ratio vias and trenches formed in connection with these shrinking device features increasingly suffer from poor step coverage of thin films, which can weaken the reliability of the integrated circuits containing them.
In response, new methods are being explored to find improved ways of metallization for integrated circuits. Metallization with copper in dual damascene structures and new low-k materials are currently among the highest priority subjects studied in integrated circuit (IC) technology. The copper metallization studies are mainly focused on single and dual damascene structures, where deposited insulator layers are patterned, vias and/or trenches are etched, surfaces of the openings are coated with a diffusion barrier and then the openings are filled with copper metal. Various shortcomings of conventional deposition techniques, e.g., physical vapor deposition (PVD) and chemical vapor deposition (CVD), are among the reasons why the copper metallization studies are concentrated on these basic structures. When the aspect ratio of the openings is over 8:1, it is very difficult to solve the step coverage problems with conventional CVD techniques, let alone PVD techniques, which can fail completely when used to process high aspect ratio vias and trenches. Consequently, alternative structures such as coaxial interconnect structures have been proposed, for example, by T. Nogami et al. in U.S. Pat. No. 6,060,383, to solve some of these problems.
Cost reduction in IC production is another challenge as more complex products with increasing numbers of transistors and interconnects require more process steps and more sophisticated and more expensive equipment for processing. This escalation in complexity has created a need for new circuit structures that can be formed with fewer process steps. Furthermore, the process steps should preferably be simpler and cheaper than those common today.
In addition, one of the most sensitive places in multi-level metallization structures is at the interface between metallization layers. In cases of insufficient bonding between metal lines and plugs, void formation easily takes place in high current applications. In addition, interface resistance exists between metallization layers on different levels because the diffusion barrier commonly between these levels typically has a resistivity of about 200–400 μΩ-cm. Undesirably, that resistivity is two orders of magnitude higher than the resistivity of copper metal.
Thus, there is a need for an improved method for processing IC structures that addresses the problems relating to the escalating numbers of process steps and the interface between metallization layers, as described above.